The DRAM pricing cycle is the load-bearing chart nobody at the AI conferences shows. It’s a ~$100 billion commodity market, dominated by three companies, that exits an oversupply trough every five-or-so years and prints generational returns when it does. The last full upcycle took Micron from roughly $10 in early 2016 to a May 2018 peak near $64 — a 5–6× run for the only US-listed pure-play. The current cycle bottomed in Q3 2023, capex was cut into 2024, and the AI server build-out is now eating supply faster than fabs can refill it. The GPU story has been priced in for two years. The memory layer underneath is still catching up.

MU

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Published$762.10·May 22·

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Data: Yahoo Finance

Micron (MU) — the only US-listed DRAM pure-play — last changed hands at $762.10 going into publication on May 22, 2026. Most of the run has already happened; that’s the point. The interesting question isn’t whether MU is cheap at the current print. It’s where the rest of the supply chain — equipment suppliers, semiconductor ETFs, and the foreign-listed names US retail mostly ignores — sits inside the same cycle, and at what point each layer turns.

Why the DRAM pricing cycle matters now

DRAM contract prices bottomed out in Q3 2023 according to TrendForce’s December 2023 release, which marked the end of an 18-month oversupply that started in Q1 2022. Samsung, SK Hynix, and Micron all cut capex aggressively through 2023. Then NVIDIA’s data-center business turned every hyperscaler’s capex plan into a memory order, and the supply side simply couldn’t respond fast enough. Fab construction takes ~20 months in Asia and ~38 months in the US — and that’s just the building. Ramping a new fab to volume production adds another 6–12 months on top.

What makes this cycle different from 2016–2018 is the mix. The press is focused almost entirely on HBM3e — the stacked, high-bandwidth memory that sits next to NVIDIA’s H100/H200/Blackwell dies. HBM commands a 3–5× ASP premium over commodity DDR5 and consumes wafer capacity at a multiple, because each HBM die is a stack of eight or twelve DRAM layers tied together by through-silicon vias. Every wafer producing HBM is a wafer not producing DDR5 for servers, laptops, and phones. The HBM bidding war between hyperscalers is tightening the commodity DRAM market by absorption, not by direct competition. Server DDR5 is firming. PC and mobile DRAM is firming. Nobody’s writing about that yet.

The arithmetic on AI server memory content is also under-discussed. A standard cloud compute server runs 16–32 DDR5 DIMMs. An AI training node — the kind sitting in a hyperscaler’s hyperscaler capex build-out — runs multiples of that, plus the HBM stacks on the accelerators. SemiAnalysis’s 2023 cost-decomposition put memory at nearly 40% of the bill of materials for an AI server with 512GB per socket — a structurally different cost profile from the standard compute boxes that came before.

How the DRAM pricing cycle actually works

The three-player oligopoly — just reordered

For 33 years, Samsung Electronics led the global DRAM market by revenue. In Q1 2025, SK Hynix overtook Samsung for the first time since 1992, capturing roughly 36% of the market versus Samsung’s 33%. Counterpoint Research’s Q3 2025 data tightened the gap (SK Hynix 34%, Samsung 33%) but the leadership change held. Micron has been the share-gainer story underneath — moving from ~22% to ~26% of global DRAM share — driven almost entirely by HBM and AI-customer alignment. CXMT, China’s state-subsidised producer, emerged at ~8% by Q3 2025 as the new fourth player.

Why the reorder matters: supply concentration still works. Three of the top four producers are publicly listed and disciplined. When all three cut capex together in 2023, supply tightened predictably. The risk to the cycle is no longer that one supplier breaks ranks during a downturn — it’s that the disciplined three become four when CXMT’s commodity DDR5 capacity reaches scale.

The capex-lag mechanism

DRAM cycles are fundamentally physical. A new fab takes years to build, costs $15–30 billion, and uses wafer-fab equipment that is itself produced by a small number of suppliers. When a downturn hits, the producers don’t shut existing fabs — they cancel the next one. That cancellation doesn’t show up in supply for two-to-three years, by which point demand has usually recovered and pricing is already firming. The lag is the cycle.

Demand by end-market

DRAM demand splits roughly four ways: PC and mobile (~40% combined), server (~35%), automotive and industrial (~15%), and other specialty (~10%). The cyclicality of the consumer buckets historically drove most of the price action. The AI cycle is shifting that gravity — server DRAM, both standard DDR5 and HBM, is becoming the marginal price-setter. When hyperscaler order books fill, suppliers prioritize server wafers and the DIMM and mobile spot markets tighten in sympathy.

HBM, DDR5, and the advanced packaging bottleneck

The DRAM node roadmap is straightforward at the top: DDR4 is now mostly a replacement market; DDR5 is the mainstream server and PC standard; HBM3e is the AI accelerator memory; HBM4 is the next step and SK Hynix’s 2026 HBM capacity is already sold out — with NVIDIA allocating roughly 70% of HBM4 orders to SK Hynix for the Vera Rubin platform. What ties all of these together is wafer capacity. Every HBM3e die is a stacked DRAM die — typically the same process node as commodity server DDR5. When a producer ramps HBM, it sacrifices DDR5 supply, and the downstream advanced packaging bottleneck means HBM cannot ramp faster than CoWoS capacity allows. Memory pricing and accelerator pricing are now mechanically linked.

Reading the leading indicator

The cleanest read on the cycle in real time is the gap between DRAM spot and contract pricing. Contract prices — the quarterly-negotiated rates that hyperscalers and OEMs pay — move slowly and lag the cycle by 1–2 quarters. Spot prices — the smaller, transactional market — move first. When spot trades meaningfully above contract for two consecutive months, contracts re-price up the following quarter. TrendForce publishes both and updates spot data twice weekly. It’s the closest thing the DRAM market has to a Bloomberg terminal, and it’s free.

Where the money flows

The investable stack splits into three layers, each leading the cycle at different timing. Naming all of them matters because the entry-and-exit characteristics are different in each.

Layer 1 — Chip makers (highest ASP leverage)

Micron Technology (MU) is the only US-listed DRAM pure-play. Its earnings move almost mechanically with blended DRAM ASP, and its HBM3e ramp has displaced Samsung as NVIDIA’s #2 HBM supplier. The trade-off: MU has the highest beta to the cycle, in both directions. Buying MU late in the upcycle has historically been the most expensive way to be right about memory.

SK Hynix (000660.KS) is non-US-listed and so practically unavailable to most US retail accounts, but it’s the load-bearing name to understand. SK Hynix held roughly 62% of the HBM market in Q2 2025, and NVIDIA accounted for ~27% of total SK Hynix revenue in the first half of 2025. When SK Hynix prints, the entire memory complex moves with it.

Samsung Electronics (005930.KS) is the under-covered narrative of this cycle. Losing DRAM leadership for the first time in 33 years is a structural story for the next two years, not a quarterly one. Samsung is investing heavily to recapture HBM share — when that capex shows up in the cycle’s supply equation matters.

Layer 2 — Equipment suppliers (leads the cycle)

Applied Materials (AMAT) and Lam Research (LRCX) are the two US-listed pure plays on DRAM capex. AMAT dominates deposition and ion implant; LRCX dominates etch — and DRAM stacking, which requires deep, high-aspect-ratio etch, is LRCX’s structural advantage. Equipment suppliers book orders 6–9 months before the fabs they sell to actually ramp production, and their P&Ls inflect 2–3 quarters before Micron’s earnings do.

Tokyo Electron (8035.T) is the third equipment name worth understanding even if it’s not in most US accounts — it owns DRAM lithography clean and is the only name with a hard monopoly position in part of the etch stack. When Tokyo Electron’s bookings move, AMAT and LRCX usually move with them within a quarter.

Layer 3 — Semiconductor ETFs (diversified exposure)

iShares Semiconductor ETF (SOXX) and SPDR S&P Semiconductor ETF (SOXQ) both hold MU, AMAT, and LRCX as top-15 positions, with SOXQ carrying a marginally lower expense ratio. Neither is a pure DRAM play — both carry heavy NVDA, AVGO, and AMD weightings, so the ETF moves capture the DRAM cycle through correlation rather than direct exposure. The trade-off is diversification: when DRAM corrects but the broader semi cycle holds, the ETFs hold up where MU drawdowns alone. They’re the right vehicle for an investor who wants memory-cycle exposure without single-name risk.

The takeaway on the three layers: equipment suppliers (AMAT, LRCX) lead the cycle by 2–3 quarters. Chip makers (MU) carry the highest ASP leverage but inflect last. ETFs (SOXX, SOXQ) blend both with broader semiconductor exposure. Each tool answers a different question about timing and concentration.

What could break this

CXMT scale-up. ChangXin Memory Technologies is no longer a future risk — it’s a present one. CXMT held ~8% of global DRAM share in Q3 2025 and is shipping DDR5-8000 and LPDDR5X-10667 modules at prices below the Korean competitors. Chinese state subsidies make profitability optional. The company’s stated capacity expansion targets 12–15% share by 2027. HBM remains insulated for now — CXMT is not competitive on the stacking and TSV steps — but commodity DDR5 server and mobile margins are already feeling the pressure.

Consumer demand staying weak. PC and mobile still represent ~40% of DRAM demand combined. If consumer device replacement cycles stay extended through 2026, the supply absorption that has been keeping the server side firm reverses. Hyperscalers can only build so many GPUs.

AI capex hangover. The largest near-term risk is one the GPU side already knows: hyperscalers over-order, then idle servers when utilization comes in below model. If 2026 builds are pulled forward from 2027, the 2027 memory order book hollows out. The shape of the AI capex curve into 2027 is the single most important macro variable for memory pricing.

Samsung breaking ranks. The Korean producer has been disciplined on supply since 2023, but that discipline isn’t permanent. Samsung has the most capacity and the most pressure to recapture share. A material pricing push from Samsung to win back HBM allocation from SK Hynix would compress margins across all three majors.

Signals to watch

Five data points reset the cycle read each quarter:

• TrendForce monthly DRAM contract price report — free, published around the 10th of each month. The cleanest read on supplier pricing power.
• Micron quarterly earnings + ASP guidance — the next print arrives late June 2026. Blended ASP, HBM revenue mix, and forward capex commentary are the three lines that move the cycle read.
• SK Hynix quarterly results — HBM3e and HBM4 supply commentary; NVIDIA-revenue concentration; capex revisions. Filed via the Korean exchange but covered well by Reuters and the FT in English.
• AMAT and LRCX bookings backlog — equipment orders are the cleanest forward indicator; when bookings flatten, the cycle is at least 6 months from rolling over.
• Samsung’s quarterly capex announcement — the swing variable on supply. Q2 and Q3 earnings calls are where this lands.

The DRAM pricing cycle has compounded fortunes and erased them on a near-decadal rhythm since the 1980s. This cycle’s distinguishing feature isn’t its existence — it’s that AI capex has shortened the lag between demand impulse and supply response from the historical 18 months to closer to nine. Memory is no longer the boring back-end of the semiconductor stack. It’s the highest-leverage call on the AI build-out that the GPU prices have already absorbed.